The memory wall is the predicted situation where improvements to processor speed will be masked by the much slower improvement in dynamic random access (DRAM) memory speed. Since the prediction was made in 1995, considerable progress has been made in addressing the memory wall. There have been advances in DRAM organization, improved approaches to memory hierarchy have been proposed, integrating DRAM onto the processor chip has been investigated and alternative approaches to organizing the instruction stream have been researched. All of these approaches contribute to reducing the predicted memory wall effect; some can potentially be combined. This paper reviews the approaches separately, and investigates the extent to which approaches can work together. The major finding is that an integrated approach is necessary, considering all aspects of system design which can impact on memory performance. Specific areas which need to be addressed include models for allowing alternative work to be scheduled while the processor is waiting for DRAM, design of virtual memory management with minimizing DRAM references a major goal, and making it possible to apply increasingly sophisticated strategies to managing the contents of caches, to minimize misses to DRAM.
@techreport{machanick-memorywall-2002,
Author = {Philip Machanick},
Institution = {University of Queensland},
Keywords = {memory wall, CPU-DRAM speedgap},
Month = {November},
Title = {Approaches to Addressing the Memory Wall},
url = {https://homes.cs.ru.ac.za/philip/Publications/Techreports/2002/memory-wall-survey/Reports/memory-wall-survey.pdf},
Year = {2002}
}