General purpose programming on graphics processing units (GPGPU) is a growing field.
GPGPU relies on high parallelism in an application domain to exploit the massive
parallelism of a GPU. However, graphics rendering is an embarrassingly parallel
problem, one where finding parallelism is extremely easy. Some stages of the graphics
pipeline can be parallelised to the pixel level – a level of parallelism not
shared by many real-world problems.
Project Crayon reconceptualizes the GPU as an array of very simple CPUs design on RISC principles. each with minimal extra features to support graphics processing. The Intel Larrabee architecture was an attempt at implementing a similar concept, but with a starting point of a Pentium pipeline, which is not competitive with simple RISC pipelines of the same era.
Why Crayon? Some of the ideas are inspired by Seymour Cray’s vector machines. I would like to call the idea a Cray on a Chip (CrayOn) but the name Cray is trademarked. As a compromise, a crayon is a graphics rendering tool of a sort – so why not Project Crayon? It does after all draw on good ideas…
To avoid confusion, the project logo is clearly a line of crayons, not a trademarked family of supercomputer companies.
A standard multicore design
Proposed Crayon design
|Conceptual design of Crayon, composed of a scaled up multicore design with a network on chip interconnect.|