CS Honours Advanced Architecture – not on offer 2021
Significant updates in progress
Watch this space for detail as the course develops. The focus of the course is
understanding fundamentals of computer architecture design using RISC-V as
- Notes are a work in progress. Download a fresh version as the course progresses.
Update 14 August 2020: Table 3.3 corrected.
Update 31 October 2019: Figure 4.6 corrected; the instruction should be addi with
-42 not subi with 42. Why? It is
unnecessary to have both instructions since the value is encoded in an immediate instruction so it can easily be
negated. It is a waste of instruction coding to have both a subtract and add immediate
Update 22 October 2019: Figures 3.2 and 4.3 corrected; typos p 36 (µs corrected to ns).
Update 18 October 2019: Exercise 1 Chapter 3 clarified; typo fixed.
Update 2 August 2019: replaced subi instruction
by addi; typo fixed; loop code fixed; pipeline examples made more consistent.
Update 1 August 2019: pipeline interlock added (pp 57–58); Table 4.1 corrected; typo fixed.
Update 22 July 2019: clarifications of register sizes.
Update 19 July 2019: minor typos fixed.
Update 16 July 2019: minor typos fixed; scalable lock references updated; exercises PDF updated.
Update 15 July 2019: 2019 updates for class use.
Update 23 November 2018: 2019 updates in progress.
Update 28 May: small typo fixed.
Update 15 May: minor corrections; more questions added, exercises available in a separate file.
Update 22 March: minor corrections; questions added to more chapters.
Update 20 March: corrections to flash section of chapter New Developments.
Update 19 March: updates to chapter New Developments.
Update 18 March: new chapter New Developments.
Update 15 March: minor update.
Update 14 March: added MESI protocol Figure; explained RISC-V alternative to atomic swap.
Update 13 March: text describing Figures 4.12 clarified.
Update 12 March: more minor fixes (Figures 4.11, 4.12).
Update 8 March, 16:21: more minor fixes.
Update 8 March, 10:21: minor fixes.
Update 6 March: pipeline chapter examples made consistent with RISC-V instruction set.
- Exercises extracted from the notes (periodically updated as the notes change)
- Additional notes
John L. Hennessy and David A. Patterson. Computer Architecture: A Quantitative Approach (5th edition), Morgan Kaufmann, 2012. ISBN 978-0123838728
Watch this space for resources.