Proc. SAICSIT '98, Gordon's Bay, South Africa, November 1998, pp 27-40

Technical Report TR-Wits-CS-1998-6

Philip Machanick and Pierre Salverda

The RAMpage memory hierarchy is an attempt at devising a comprehensive strategy to address the growing DRAM-CPU speed gap. By moving the main memory up a level to the SRAM currently used to implement the lowest-level cache, a RAMpage system in effect implements a fully associative cache with no hit penalty (in the best case). Ordinary DRAM is relegated to a paging device. This paper shows that even with an aggressive SDRAM conventional main memory (or equivalently the new Direct Rambus design proposed for 1999), a RAMpage hierarchy is over 16% faster than a conventional 2-level cache design, with a high-end CPU of a speed likely to be delivered in 1998. Further optimizations of the RAMpage hierarchy, such as context switches on misses, are likely to further improve this result.

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